ShieldSigner — modular Luckfox smartcard carrier

Main PCB: eight-pin 2.8-inch, four-layer carrier. Open it with mise run kicad:open; validate it with mise run kicad:check. The former 40-pin FPC design is preserved in variants/standard-fpc/kicad/. Current assembly/review metadata remains under variants/lcd-module-2.8/; its kicad link is a compatibility alias to the main project.

Native KiCad is the preferred editing workflow. This repository publishes the reviewed ShieldSigner carrier variant, tools and knowledge site. Separate experimental tscircuit ports preserve the standard carrier and current pill carrier for comparison.

Hardware component PDFs are collected in the top-level datasheets directory. The current display/button electrical review records wiring, startup checks and first-article tests.

Firmware and repository navigation

• Firmware artifacts: one home for verified images, staging, reusable build data and provenance; find the current image with mise run firmware:where.
• LVGL firmware: runtime architecture, memory work and scoped hardware/fixture validation.
• Repository cleanup goal: phased organization work and acceptance checks that preserve the working build.

Eight-pin 2.8-inch pill build

Working PCB: 0.0.11-dev. Four copper layers with two GND planes, eight factory-assembled Keystone 5015 service points, four additional M2.5 bracket mounts and a readable native schematic. The current kit has 43 SMT placements / 18 SKUs. J302 is removed; TP901/TP902 provide bench +5V/GND. See the service revision. Supplier review is required, and the selected switches/reader IC/socket currently lack standard assembly stock. Released 0.0.9 ZIPs remain historical two-layer files.

The historical PCB 0.0.9-dev added the official The Space logo and denver.space rear silkscreen. The artwork audit confirms every non-silkscreen PCB object is unchanged from 0.0.7. The matched 35-part/17-SKU kit passes native electrical, pinout and manufacturing-file checks. Five assembled boards are not checkout-ready: fresh JLC assembly stock lists only two selected smartcard sockets, and this revision needs a new supplier placement/DFM review. See order readiness.

Use carrier-profile firmware before power-up. The working 240×240 bench image drives two carrier button nets as LCD outputs. The compatibility audit maps every pin and explains the required 320×240/10 MHz carrier configuration. The board keeps its always-on backlight default.

Start with the pill carrier guide and customer assembly steps. This 160×70 mm capsule follows the eight-pin SPI module interface in the existing Luckfox design, with the larger 2.8-inch display between the controls. The current factory assembly BOM specifies 43 SMT placements across 18 catalog lines. Customer soldering is ordinary headers: 30 carrier joints, plus up to 30 if both modules arrive bare.

The PCB uses a dedicated 3.3 V display regulator, supported display mounts and 23 local 3D models. Native ERC/DRC/connectivity/parity pass with zero exclusions. Open with mise run variant:lcd:open; build matched prototype quote files with mise run variant:lcd:fab. Physical fit, firmware/display behavior and powered bring-up remain unqualified.

The former 0.0.3-dev Pico-format display bay is superseded. Sections below also retain the separate standard FPC carrier and its experimental tscircuit port; do not mix their manufacturing files with the pill kit.

The printed enclosure guide includes the screw list, camera clamp, button mechanisms and first-fit checks. Inspect the assembled and exploded models on the site. The enclosure prototype release contains portable STL, SCAD and 3MF files for the 0.0.6-dev PCB. Run mise run enclosure:verify to regenerate and check the case.

The optional DigiKey self-assembly guide provides a separate purchase BOM for the same pill board. JLC remains the primary PCBA route.

Backlight PWM revision candidate

The 0.0.10-dev backlight candidate adds a dedicated Luckfox PWM path and one pull-down resistor. Always-on remains the factory default; PWM is selected with the existing backlight straps. Native ERC/DRC/connectivity/parity and both mode checks pass. This candidate is separate from the main 0.0.9 artwork/ordering kit; neither new revision has a current cart approval; module PWM response still needs a bench check. Rebuild it with mise run variant:lcd:pwm.

Standard FPC reference documentation

Read these in order:

1. Electrical review: checked circuitry, corrected reset interpretation and open bench/assembly items.
2. JLCPCB BOM plan and sourcing table: 43 carrier placements, exact catalog identities and dated availability.
3. Bring-up guide and results template: staged prototype measurements and tests.
4. Smartcard choices: contact compatibility, SeedKeeper versus Satochip, DIY and conditional applets.

The component guide covers all 53 PCB references and pad/net maps. Hardware guide explains the blocks; port status explains the experimental tscircuit limitations. Native KiCad is the preferred workflow.

Historical standard FPC workflow

See KiCad setup, exports and remaining DRC work. Use mise run kicad:standard:check for the preserved historical project. The default kicad:* commands target the main eight-pin carrier. The native schematic has zero ERC errors/warnings. The PCB has zero active DRC errors/warnings and zero unconnected/parity issues. Two documented courtyard exceptions apply only to mutually exclusive DNP mode straps; population checks enforce that assumption.

Experimental tscircuit workflow

mise install [email protected] [email protected]
mise run setup
mise run generate
mise run docs
mise run build
mise run check
mise run dev

generate requires uv and regenerates geometry from the current native KiCad PCB, recording its SHA-256. Builds/checks reject stale extracted data. src/ShieldSignerPlus.tsx defines the native board. scripts/build.tsx verifies every physical pad against the reference before attaching the original tracks, vias, and filled copper. src/index.tsx exposes the native components for tscircuit preview. mise run dev regenerates/builds and previews routed circuit JSON on /downloads/ After changing KiCad or TSX, run generate/build again to refresh that output. mise run dev:source previews editable TSX without imported copper on port 3022.

Outputs in dist/: circuit JSON, top/bottom PCB SVGs, schematic SVG, and BOM JSON. The schematic is a generated connectivity view, not a reproduction of the original schematic sheet arrangement. Components use generic chip symbols with original values and pin aliases.

The current 0.0.9 pill carrier has a source-authored tscircuit design at src/PillCarrier.tsx. Run mise run tscircuit:pill:check to build and validate it, then mise run tscircuit:pill:dev for the editable source preview on port 3020. Resistors, capacitors, switches, connectors and solder jumpers use their native component primitives. Seven functional schematic sheets, reusable footprint components, editable silkscreen, local 3D models, fresh autorouting and copper pours compile directly from TSX. Builds do not read KiCad or geometry snapshots. Outputs and the portable source ZIP are under dist/pill-native/.

The earlier exact-copper reference renderer remains at src/PillCarrierReference.tsx, with tscircuit:pill:reference:build/check/dev tasks and outputs under dist/pill-tscircuit/. See scope, validation and upstream limitations.

Standard FPC hardware reference

Pinned upstream commit: efdd1cfd14e80a076a7e1ae91e9f2270ecbcd44f in 3rdIteration/seedsigner. Original board, hierarchical schematics, README, license and provenance are in reference/.

The port contains 53 components, 86 named nets (including unconnected physical pin groups), 479 tracks, 314 vias, and 33 filled copper polygons. It includes the SEC1210 smartcard interface, combined SIM/full-size card socket, USB-C power, buttons, and 40-pin 2.8-inch ST7789 LCD interface. Use the upstream BOM and assembly instructions to select exact parts. The Luckfox Pico mounts microSD side upward, USB end toward the edge; insulate protruding pins beneath the LCD and follow the reference jumper defaults.

The OS compilation guide records pinned inputs, the Proxmox builder setup, build commands, monitoring and artifact retrieval. See the bring-up guide for hardware and first boot. Firmware selection and secure boot are separate from the PCB port. B13's signed Mini SD image uses a public development key; signing alone does not enable secure boot. Do not fuse a device as part of PCB setup.

Validation and limitations

The build writes dist/validation-report.json with preserved renderer warnings and the exact validation scope. The port checks physical land coordinates/polygons and preserves original copper rather than invoking a new autorouter. Roundrects and board arcs are polygon approximations; a 0.02 mm tolerance closes tiny source outline gaps. Original silkscreen, paste-only exposed-pad stencil subdivisions, full manufacturing stackup and fabrication outputs have not been migrated. Two known component body bounding-box warnings (SW503 and U202 near the module notch) are excluded from compiled output; actual pad geometry is still checked. This is a reproducible editable port and preview, not a manufacturing sign-off. Review the original KiCad design and run manufacturing DRC before ordering.

Public documentation website

shieldsigner.dev presents the hardware, smartcards, firmware and build guides. The static website implementation and deployment guide follows the SeedPills Caddy pattern. Public HTML and assets are generated from these docs; private ingestion data is excluded.

License and provenance

Derived from 3rdIteration/SeedSigner at the pinned revision in reference/provenance.json. The upstream MIT notice is retained in LICENSE. Supplier PDFs remain their publishers’ documents; footprint-library notices are retained in place. This is a development variant, not a tested production signer.

Public repository

Canonical source: lightningspore/shieldsigner-dev. See the build overview for the broader module/camera/case/firmware workflow. The 0.0.9-dev pill package contains the current native project, schematic, matched quote kit and 3D exports. The older workflow preview remains a separate standard FPC reference. These are prototype review files, not physically qualified production hardware.

Build and use workflows

The public site now starts with six tasks: PCB order, parts, compile, flash, SeedSigner use and smartcards. The website development version and source revision are visible in its footer. Passives show explicit units and catalog ratings. For the standard FPC reference, mise run bom:check validates its 28 fitted passive values. The pill manufacturing gate validates its own fitted passives against its catalog. C603/C604 purchase identities are now the 1 µF C28323 parts, superseding the initial preview’s incorrect 100 nF metadata.

Revision 0.0.6-dev replaces the eight XKB switches with C&K PTS636SK25SMTRLFS and the SHOUHAN USB-C with GCT USB4125-GF-A-0190, using new manufacturer lands and exact shared JLC/DigiKey MPNs. Use its matched BOM/CPL and Gerbers together. The mechanical review records the baseline comparison; self-assembly documentation explains sourcing and measured-height plungers.

Source: README.md ↗. Documentation describes reviewed evidence; it does not replace physical testing.