TASK 01
Make & order the PCB
Review the matched 0.0.11 artwork package, resolve socket stock, and request a fresh assembly preview/quote.
You need
- Eight-pin pill carrier selected
- JLCPCB account for a prototype quote
You’ll have
Gerbers + matching BOM/CPL ready for a reviewed prototype quote.
PCB 0.0.11-dev is stock_review_required: exact switch, socket and UR2 reader sourcing, new supplier placement/DFM review, stackup and panel/tooling approval remain required before checkout. Old cart/preview evidence is historical.
Download JLC order files ↓Open JLCPCB quote ↗Pill Gerbers + BOM + CPL · 4 layers · 1.6 mm · 160 × 70 mm
CARRIER PCB · 0.0.11-dev
Inspect both sides.
Large, straight-on views with component bodies hidden. Four copper layers, factory Keystone service points and four additional M2.5 bracket holes. Open either image at full size to zoom in. Check current order readiness →
Top · display & buttons
Eight button positions, the display header and its dedicated 3.3 V regulator.
PCB only · component bodies hiddenCopper & silkscreen drawing (SVG) ↗
Bottom · reader & power
Luckfox connections, the relocated smartcard circuit, USB-C power and labelled test pads.
PCB only · component bodies hiddenCopper & silkscreen drawing (SVG) ↗
Choose the assembled pill carrier
- The 160×70 mm pill uses a 2.8-inch eight-pin SPI module, socketed Luckfox and contact smartcard reader.
- Recommended route: JLCPCB assembles 43 SMT placements; you install ordinary headers, modules and screws.
- These files supersede the Pico-format display bay. The standard FPC carrier remains a separate reference.
- Current order target is main 0.0.11-dev, with four copper layers, factory Keystone service points, bracket holes and the existing always-on backlight. The separate PWM candidate is not promoted.
Download the matching order files
- Use the 0.0.11 pill bundle as one set. Its Gerbers/BOM/CPL share the new PCB hash and datum; do not reuse the old 0.0.7 preview as approval.
- Unzip once. Upload the inner shieldsigner-modular-gerbers.zip for the PCB; upload bom-jlcpcb.csv and cpl-jlcpcb.csv for assembly.
- LCD, Luckfox, customer headers/supports, six copper jumpers and twelve copper test pads are outside the SMT BOM. J302 is the optional 5 V/GND power header; old FPC/backlight parts are absent.
Upload Gerbers to JLCPCB
- Start a PCB quote and upload the Gerber ZIP, not the KiCad source ZIP.
- Confirm a 160×70 mm capsule, two copper layers and 1.6 mm thickness. Inspect the preview and separate plated/nonplated drills.
- Enable PCB assembly for PCBA. The carrier uses parts on both sides; confirm the quoted assembly service supports them.
Match parts and inspect placement
- Upload matching BOM/CPL. Expect 43 fitted SMT references across 18 catalog identities.
- C603/C604 remain 1 µF C28323; C701/C702 are 10 µF C15850; U701 is the 3.3 V AP2112K C51118; U601 is the UR2 C633309.
- Inspect both sides, card entrance, USB direction, SEC1210/regulator pin 1 and eight switches. No substitutions without checking electrical and footprint compatibility.
- The current exact-MPN snapshot has no standard assembly stock for the selected switches, socket and SEC1210/PV-UR2. Confirm exact sourcing, MOQ, lead time and attrition with the supplier; overseas inventory is separate.
- Five assembled units are not checkout-ready until JLC confirms enough exact sockets and attrition. Two visible sockets do not guarantee two assembled units; no substitute or lower quantity is assumed.
- J301 USB4125-GF-A-0190 may need explicit selection if the BOM importer leaves it unchecked. The compensated CPL already includes J301/J601/U601 origin/rotation corrections: do not repeat old manual moves.
Resolve the remaining quote/DFM items
- Obtain a fresh 0.0.11 supplier preview and final DFM/placement confirmation, approved assembly rails/fiducials/tooling, enough exact socket stock plus attrition, and a new quote before payment.
- Check the purchased LCD J1 row, mounting dimensions and 12 mm support stack. The retail module is outside PCBA.
- These are prototype quotation files. Native ERC/DRC/connectivity/parity pass with zero exclusions; physical fit, display power/thermal behavior, firmware and enclosure testing remain open.
- Before module power-up, use a reviewed carrier-profile image. The tested base-fork bench image drives GPIO56/57 as LCD outputs, but those are Left/Up switches on this PCB; pressing a switch can ground a driven output.
If you change the board, regenerate everything
- Use KiCad 10 and the local libraries. Run these commands from the repo root.
- Inspect the exported preview before using the regenerated order files.
Regenerate checks and manufacturing files
mise run variant:lcd:check
mise run variant:lcd:models
mise run variant:lcd:fab
mise run variant:lcd:review
mise run variant:lcd:packageSources & deeper reference
Checked 12 October 2026. Menu names can vary with firmware.
Pill design and rationale ↗BOM and dated stock ↗Practical build checks ↗Optional DigiKey self-assembly ↗Current first-article readiness ↗Carrier firmware profile compatibility ↗Edit this workflow on GitHub ↗